1. Field of the Invention
This invention relates generally to electronic systems involving memory devices. More particularly, this invention relates to various techniques to optimize information transfers over interconnect resources in such systems.
2. Description of the Related Art
The design and fabrication technology of semiconductor memory devices has evolved rapidly over the past decade. In the case of dynamic random access memories (DRAMs), for example, the number of bits of data stored in a single DRAM chip has increased by a factor of four roughly every three years. This has resulted in the doubling of the size of memory systems at the same rate. Each new higher density generation of DRAMs reduces the number of individual memory chips needed in a system by one half. Fewer (but higher density) individual DRAM chips in memory systems results in fewer total number of pins available for transfer of data within the system. Reducing the number of pins available for receiving and transmitting information decreases the bandwidth of the memory system. That is, while internal to the memory chip large numbers of bits can be accessed per cycle, only a small percentage of the data can make it across the device boundary to the external world in any given time interval.
Todays advanced computing systems and microprocessors, however, demand greater and greater data bandwidths from memory systems. This has resulted in a more concerted effort in the memory industry to devise solutions to the bandwidth bottleneck. One approach to improving the data bandwidth in memory systems has focused on designing high speed interface structures. A memory sub-system based on a very fast and efficient interface technology that exploits a number of innovative data transmission techniques is described in U.S. Pat. Nos. 5,319,755 (Farmwald et al.) and 5,430,676 (Ware et al.). Other prior art approaches have focused more on the internal circuitry of the memory devices to increase the rate of data transfer.
While prior art techniques have improved the data bandwidth of memory systems, there is a need for further improvement as the demand for ever greater data bandwidth continues to grow.
The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to increase data bandwidth. Broadly, the invention offers solutions to the problem of packing all of the required information including data, control and address information over a limited number of interconnect wires in an optimized fashion. In one embodiment, the present invention combines different address information such as row address and bank address information into a unified address field wherein one or more bits can be shared. By sharing bits across various address fields, the present invention conserves bandwidth that is required by the control signals. In another embodiment, the present invention provides various schemes for defining and constructing packets of information that maximize the amount of information carried by a given packet across a limited number of interconnect wires.
Accordingly, in one embodiment, the present invention provides an electronic system including a master controller and at least one memory device coupled to the master controller via an interconnect structure, with the interconnect structure having a multi-wire bus for carrying control information from the master controller to the memory device, wherein, the control information comprises control information of a first type and control information of a second type, and wherein, the control information of the first type is merged with the control information of the second type to form a combined control information field requiring fewer interconnect wires.
In another embodiment, the present invention provides an electronic system including a master controller and at least one memory device coupled to the master controller via an interconnect structure, with the interconnect structure having a multi-wire bus for carrying control information from the master controller to the memory device, wherein the memory device comprises framing circuitry to establish framing of a first group of signals in relation to framing information from a second group of signals.